1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with an internal clock generation circuit operating in synchronization with a rise and a fall of an external clock and generating an internal clock synchronized with the external clock.
2. Description of the Background Art
Generally, an SDRAM (Synchronous Dynamic Random Access Memory) operating in synchronization with an external clock includes therein a clock generation circuit which generates an internal clock synchronized with the external clock. Using this internal clock, an internal circuit in SDRAM is controlled.
More specifically, a circuit controlling data input/output for SDRAM to communicate data with the outside is also controlled by this internal clock. Therefore, the timing of data input/output is largely affected by the phase accuracy of the internal clock.
Meanwhile, by the demand for a higher frequency operation of a semiconductor device, a DDR SDRAM (Double Data Rate SDRAM) is developed and brought into practical use, in which data is input/output in synchronization with rising and falling edges of an external clock. In this DDR SDRAM, it is particularly demanded to further reduce a phase difference between an edge of an external clock and data input/output timing for DDR SDRAM, as compared with a conventional SDRAM. Specifically, since DDR SDRAM allows data input and output at a frequency rate double the conventional SDRAM, the phase shift between the edge of the external clock and the data input/output timing is larger relative to the period of the external clock.
FIG. 12 is a timing chart showing data output timing in reading data from a DDR SDRAM, that is a so-called DDR-I. In this DDR SDRAM, a CAS latency CL is set at 2.5 and a burst length BL is set at 4. The CAS latency represents here the number of cycles (one cycle corresponds to the time period from a rise of an external clock EXTCLK to the next rise) for the DDR SDRAM to receive a READ command (a command for reading data) from the outside and then to start to output the read data to the outside. The burst length represents the number of bits successively read out in response to READ command.
Referring to FIG. 12, DDR-I outputs data DQ of the read data and a data strobe signal DQS in synchronization with external clocks EXTCLK, EXT/CLK. The external clock EXT/CLK here is a clock signal complementary to the external clock EXTCLK. The data strobe signal DQS is used as a timing to take in data DQ on the side of an external controller receiving data DQ.
A timing difference tAC between the edges of external clocks EXTCLK, EXT/CLK and the output of data DQ is defined to fall within a certain range. In FIG. 12, timing difference tAC is controlled to be zero. Furthermore, an output timing difference tDQSQ between data strobe signal DQS and data DQ also needs to fall within a certain range.
In addition, in DDR-I, data strobe signal DQS in reading data is defined to be generated (CAS latency CL-1) cycle before data DQ starts to be output. This period is called xe2x80x9cpreamblexe2x80x9d. It is also defined that data strobe signal DQS is at L (logic low) level during half cycle after the final data of data DQ starts to be output. This period is called xe2x80x9cpostamblexe2x80x9d.
In order to realize a data output as shown in FIG. 12, an operation clock is required of which timing is slightly earlier than that of the edge of external clock EXTCLK, in a data output circuit. This is because a delay is occurred before data is actually output after an external clock is input into a semiconductor memory device, because of a capacitance of each internal circuit.
More specifically, what is needed is a clock generation circuit operating in a manner as follows. As external clock EXTCLK is a fixed cycle signal, internal clocks CLK_P, CLK_N shifted backward by an adequate amount of time Ta with respect to the edge of external clock EXTCLK are generated by delaying external clock EXTCLK by an adequate amount of delay Td. Furthermore, delay amount Td can be controlled such that data DQ output from the data output circuit and data strobe signal DQS output from a data strobe signal output circuit, which operate triggered by these internal clocks CLK_P and CLK_N, satisfy the differences tAC and tDQSQ described above. A circuit that generates such an internal clock is called a DLL (Delay Locked Loop) circuit.
The backward amount Ta is determined from a propagation time from taking in the read data triggered by internal clocks CLK_P, CLK_N to ultimately reading out the read data to a data output terminal. Then, as shown in FIG. 12, when CAS latency is 2.5, the first data of data DQ is output in synchronization with the rising edge of EXT/CLK (the falling edge of EXTCLK), and thereafter odd numbered data and even numbered data of data DQ are sequentially output to the outside, respectively triggered by internal clocks CLK_N and CLK_P.
FIG. 13 is a schematic block diagram conceptually illustrating an overall configuration of an READ-related circuitry operating with an internal clock generated in the DLL circuit described above.
Referring to FIG. 13, a DLL circuit 100 outputs an internal clock CLK_PF generated by delaying external clock EXTCLK and an internal clock CLK_NF generated by delaying external clock EXT/CLK. A repeater 120 receives internal clocks CLK_PF and CLK_NF distributed from DLL circuit 100 and outputs them as DLL clocks CLK_P and CLK_N.
A plurality of data output circuits 200 are provided based on a word organization to which DDR SDRAM corresponds. Here, sixteen data output circuits 200 outputting data DQ0-DQ15 are provided. Each data output circuit 200 receives DLL clocks CLK_P and CLK_N output from repeater 120, is activated by either of DLL clock CLK_P or CLK_N selected based on an internal signal NZPCNT received from a READ control circuit 400, and takes in and externally outputs data read from a memory cell array onto a data bus.
As shown in FIG. 13, a signal path from DLL circuit 100 to data output circuits 200 is generally formed like a tree. The circuits and signal lines are arranged such that the data output timings do not vary among a plurality of data output circuits 200. A repeater 120 is generally arranged for every eight data output circuits or every four data output circuits.
A data strobe signal output circuit 500 generates and externally outputs data strobe signals LDQS and UDQS which indicate of timing for externally outputting the read data output from data output circuit 200. Data strobe signal output circuit 500 receives DLL clocks CLK_P and CLK_N output from repeater 120, generates data strobe signals LDQS and UDQS during the period from preamble to postamble using an internal signal QSOE received from READ control circuit 400, in synchronization with DLL clocks CLK_P and CLK_N, and externally outputs the generated data strobe signals LDQS and UDQS.
READ control circuit 400 operates in synchronization with internal clocks CLK_PF and CLK_NF received from DLL circuit 100, generates a variety of signals required for a data reading operation in response to READ command, and outputs the signals to data output circuit 200 and data strobe signal output circuit 500. Internal signals QSOE, DOE, EZORG, RDETG and NZPCNT will be described later in the description of data output circuit 200 and data strobe signal output circuit 500 using these signals.
FIG. 14 is a functional block diagram illustrating DLL circuit 100.
Referring to FIG. 14, DLL circuit 100 includes variable delay circuits 206 and 208, pulse generation circuits 210 and 212, an input/output replica circuit 214, a phase comparator 216 and a delay control circuit 218.
An input buffer 202 receiving external clocks EXTCLK and EXT/CLK input from the outside and outputting an internal clock BUFFCLK_DLL to DLL circuit 100 detects a cross point between a potential level in the rise of external clock EXTCLK and a potential level in the fall of the inverted signal thereof, external clock EXT/CLK, and generates internal clock BUFFCLK_DLL. On the other hand, an input buffer 204 detects a cross point between a potential level at which external clock EXTCLK falls and a potential level at which an external clock EXT/CLK rises, and generates an internal clock BUFF/CLK_DLL.
Variable delay circuit 206 delays internal clock BUFFCLK_DLL received from input buffer 202 to be output to pulse generation circuit 210. Variable delay circuit 206 includes a plurality of delay units generating delays, and delays internal clock BUFFCLK_DLL by connecting/disconnecting the delay units based on an instruction from delay control circuit 218.
Pulse generation circuit 210 generates internal clock CLK_PF as a pulse signal synchronized with a rising edge of a signal output from variable delay circuit 206.
Variable delay circuit 208 delays internal clock BUFF/CLK_DLL received from input buffer 204 to be output to pulse generation circuit 212. The configuration of variable delay circuit 208 is same as that of variable delay circuit 206 and therefore description thereof will not be repeated.
Pulse generation circuit 212 generates internal clock CLK_NF as a pulse signal synchronized with a rising edge of a signal output from variable delay circuit 208.
Input/output replica circuit 214 reproduces in a simulated manner input buffer 202 and circuit characteristics from internal clocks CLK_PF and CLK_NF being output from DLL circuit 100 to data DQ being output to a data input/output terminal, and applies in a simulated manner the delay amount created in these circuits to internal clock CLK_PF.
Phase comparator 216 compares the phases between internal clock FBCLK output from input/output replica circuit 214 and internal clock BUFFCLK_DLL after one cycle or few cycles, and generates control signals UP and DOWN for increasing/decreasing the delay amount of variable delay circuits 206 and 208 based on that phase difference.
Delay control circuit 218 adjusts the delay amount in variable delay circuits 206 and 208 by generating a delay control signal based on control signals UP and DOWN and outputting the same to variable delay circuits 206 and 208. When the phases match between internal clock BUFFCLK_DLL and the internal clock FBCLK, neither control signal UP nor DOWN is output from phase comparator 216, the delay control signal is of a fixed value, and thus the delay amount in variable delay circuits 206 and 208 is fixed.
Therefore, internal clocks CLK_PF and CLK_NF has a phase earlier than external clocks EXTCLK and EXT/CLK by the sum of the delay amount from DLL circuit 100 to data output circuit 200 and the data output delay amount in data output circuit 200. Accordingly, when the delay amount applied in input/output replica circuit 214 matches the delay amount in input buffer 202, repeater 120 and data output circuit 200, the timing difference tAC described above is zero.
On the other hand, when the phases do not match between internal clock BUFFCLK_DLL and internal clock FBCLK, control signal UP or DOWN is output from phase comparator 216 according to the phase difference, and the delay amount is adjusted by connecting/disconnecting the delay units in variable delay circuits 206 and 208.
FIG. 15 is a circuit diagram showing a circuit configuration of repeater 120.
Referring to FIG. 15, repeater 120 is configured with inverters 1202-1208. Repeater 120 receives internal clock CLK_PF and outputs DLL clock CLK_P through inverters 1202 and 1204. Furthermore, repeater 120 receives internal clock CLK_NF and outputs DLL clock CLK_N through inverters 1206 and 1208.
FIG. 16 is a functional block diagram illustrating data output circuit 200.
Referring to FIG. 16, data output circuit 200 includes amplifier circuits 362 and 364, a parallel/serial conversion circuit 366, an output data latch circuit 302, an output driver circuit 304 and a clock select circuit 220.
In case of DDR-I described above, reading data from the memory cell array every one cycle is premised on a two-bit prefetch operation in which data of two bits is read for each data output circuit in a single readout. More specifically, data of two bits is read from the memory cell array to data output circuit 200 at one time every one cycle. The data of two bits is ordered in data output circuit 200 and is transferred every half cycle to be output to the outside.
Amplifier circuits 362 and 364 receive an internal signal RDETG output from READ control circuit 400. Amplifier circuit 362 is connected to a data bus pair DB0 and /DB0 and amplifier circuit 364 is connected to a data bus pair DB1 and /DB1 while internal signal RDETG is at H (logic high) level. Internal signal RDETG is a signal for taking in data from the data bus pair in amplifier circuits 362 and 364 and is controlled in READ control circuit 400 such that it goes to H level at a prescribed timing.
Amplifier circuit 362 operates every one cycle in synchronization with DLL clock CLKQ output from clock select circuit 220, reads data read out from the memory cell array onto the data bus pair DB0 and /DB0, and amplifies the signal level of the read data for outputting to parallel/serial conversion circuit 366. Similar to amplifier circuit 362, amplifier circuit 364 operates every one cycle in synchronization with DLL clock CLKQ, reads data read out from memory cell array onto the data bus pair DB1 and /DB1 at the same timing as the data read out onto the data bus pair DB0 and /DB0, and amplifies the signal level of the read data for outputting to parallel/serial conversion circuit 366.
Similar to amplifier circuits 362 and 364, parallel/serial conversion circuit 366 operates every one cycle in synchronization with DLL clock CLKQ, receives data RD0 and /RD0 (which are complementary signals and one-bit data) and data RD1 and /RD1 respectively output from amplifier circuits 362 and 364, and orders data RD0 and /RD0 as well as data RD1 and /RD1 based on internal signal EZORG output from READ control circuit 400 for outputting to output data latch circuit 302. Here, internal signal EZORG reflects information of the least significant bit CA0 of a column address applied simultaneously with READ command and is generated in READ control circuit 400 based on CA0.
Output data latch circuit 302 receives and latches data RDD, /RDD output from parallel/serial conversion circuit 366, and transfers the data to output driver circuit 304 bit by bit, in synchronization with DLL clocks CLK, /CLK0 output from clock select circuit 220 and operating every half cycle. Output driver circuit 304 then outputs data DQi to the outside through a data input/output terminal 18.
Clock select circuit 220 generates DLL clock CLKQ activating amplifier circuits 362 and 364 and parallel/serial conversion circuit 366 as well as DLL clocks CLKO, /CLKO activating output data latch circuit 302, based on DLL clocks CLK_P and CLK_N.
As described above, DDR-I employs a two-bit prefetch configuration in which data of two bits read every one cycle is transferred serially to output driver circuit 304 every half cycle, and therefore clock select circuit 220 needs to generate DLL clock CLKQ starting from either DLL clock CLK_P or CLK_N according to the first data output timing.
Accordingly, clock select circuit 220, in view of CAS latency defining the first data output timing, generates DLL clock CLKQ by selecting either internal clock CLK_P or CLK_N based on internal signal NZPCNT having different logic levels depending on whether CAS latency is an integer or a half-integer, and outputs the same to amplifier circuits 362 and 364 and parallel/serial conversion circuit 366 to activate these circuits.
Clock select circuit 220 also generates DLL clocks CLKO, /CLKO which trigger data RDD, /RDD received by output data latch circuit 302 from parallel/serial conversion circuit 366 to be transferred to output driver circuit 304 bit by bit every half cycle. DLL clock CLKO is a clock signal formed by OR of DLL clocks CLK_P and CLK_N. DLL clock /CLKO is a signal complementary to DLL clock CLKO.
In this way, data DQ is output from data output circuit 200 at the timing shown in FIG. 12.
As described above, for data DQ in order to be taken in at the outside of the device, data strobe signal DQS output in synchronization with data DQ needs to be referred to externally.
FIG. 17 is a functional block diagram illustrating data strobe signal output circuit 500. In FIG. 13, two data strobe signals LDQS and UDQS respectively corresponding to the lower bit and the upper bit of the output data DQ are output from data strobe signal output circuit 500. Although separate circuits are provided for outputting these two signals, only a circuit for either one of signals is shown in FIG. 17 as the circuit configurations are same.
Referring to FIG. 17, data strobe signal output circuit 500 includes a QSOE shift circuit 502, an output data generation circuit 504, an output data latch circuit 506, an output driver circuit 508 and a clock generation circuit 510.
Clock generation circuit 510 receives DLL clocks CLK_P and CLK_N output from repeater 120 and further receives an internal signal DOE output from READ control circuit 400, and generates control clocks CQP and CQN activating QSOE shift circuit 502 and output data generation circuit 504 as well as DLL clocks CLKO and /CLKO activating output data latch circuit 506. Here, internal signal DOE is a signal that goes to H level during READ operation.
QSOE shift circuit 502 receives internal signal QSOE output from READ control circuit 400 and generates signals QSOE1 and QSOE2 by shifting internal signal QSOE by a prescribed amount in synchronization with control clocks CQP and CQN output from clock generation circuit 510.
Here, internal signal QSOE is a signal for determining a column activation period based on burst length BL and goes to H level during (burst length BL/2) cycle after receiving READ command. The generated signal QSOE1 is a signal for determining the preamble period. Signal QSOE2 is a signal for determining the period in which a transition of data strobe signal DQS takes place in synchronization with data DQ.
Output data generation circuit 504, in synchronization with control clocks CQP and CQN output from clock generation circuit 510, generates data RDA and /RDA for generating data strobe signal DQS from the start of the preamble period to the end of the postamble period, based on signals QSOE1 and QSOE2 output from QSOE shift circuit 502.
Output data latch circuit 506 and output driver circuit 508 operate every half cycle in synchronization with DLL clocks CLKO and /CLKO output from clock generation circuit 510. Output data latch circuit 506 and output driver circuit 508 have the same circuit configurations as output data latch circuit 302 and output driver circuit 304, respectively, in data output circuit 200 shown in FIG. 16.
As described above, ideally, there is no phase difference between the outputs of data DQ and data strobe signal DQS. Practically, the output timings of these signals need to be controlled such that timing difference tDQSQ between both signals falls within a prescribed time. Therefore, also in output data latch circuit 506 in data strobe signal output circuit 500, DLL clocks CLKO and /CLKO generated from DLL clocks CLK_P and CLK_N serve as the output trigger for data strobe signal DQS in a manner similar to output data latch circuit 302 in data output circuit 200.
In practice, output data latch circuit 506 and output driver circuit 508 are configured to include transistors having the same dimensions as output data latch circuit 302 and output driver circuit 304 in data output circuit 200, and in addition they are designed such that timing difference tDQSQ is as small as possible for example by sharing a common configuration layout.
FIGS. 18 and 19 are circuit diagrams showing a circuit configuration of clock generation circuit 510.
Referring to FIGS. 18 and 19, clock generation circuit 510 includes a first internal circuit 510A and a second internal circuit 510B. The first internal circuit 510A includes a /CLK_PE generation circuit 512 and a /CLK_NE generation circuit 514. The second internal circuit 510B includes a CLKO generation circuit 516, a CQP generation circuit 518 and a CQN generation circuit 520.
Referring to FIG. 18, /CLK_PE generation circuit 512 includes NAND gates 5121-5123, delay circuits 5124-5126 and inverters 5127-5129.
/CLK_PE generation circuit 512 generates a falling pulse signal /CLKF_P having the pulse width of delay time by delay circuit 5125 in synchronization with the rising edge of DLL clock CLK_P when internal signal DOE is at H level. Furthermore, /CLK_PE generation circuit 512 generates a falling pulse signal /CLK_PE having the pulse width of the delay time by delay circuit 5126 plus the delay time by delay circuit 5125 in synchronization with the rising edge of DLL clock CLK_P.
In the following, the operation of /CLK_PE generation circuit 512 will be described.
When internal signal DOE is at H level, NAND gate 5121 acts as an inverter, and DLL clock CLK_P is delayed at delay circuit 5124 and inverted by inverter 5127 to be output to node N1. Delay circuit 5125, inverter 5128 and NAND gate 5122 output to node N2 a falling pulse corresponding to the delay time by delay circuit 5125, synchronized with the rising edge of the signal at node N1, thereby resulting in signal /CLKF_P. NAND gate 5123 then receives signal /CLKF_P and a signal produced by delaying signal /CLKF_P at delay circuit 5126 and outputs a signal being at H level from the falling edge of signal /CLKF_P to the rising edge of the delayed signal of signal /CLKF_P. The signal output from NAND gate 5123 is then inverted by inverter 5129, thereby resulting in signal /CLK_PE.
/CLK_NE generation circuit 514 includes NAND gates 5141-5143, delay circuits 5144-5146 and inverters 5147-5149. /CLK_NE generation circuit 514 generates falling pulse signals /CLKF_N and /CLK_NE from DLL clock CLK_N when internal signal DOE is at H level, similar to /CLK_PE generation circuit 512. The circuit configuration of /CLK_NE generation circuit 514 is same as that of /CLK_PE generation circuit 512 and therefore description thereof will not be repeated.
Referring to FIG. 19, CLKO generation circuit 516 includes an NAND gate 5161 and inverters 5162-5167. CLKO generation circuit 516 generates DLL clock CLKO and DLL clock /CLKO complementary thereto synchronized with the falling pulse signals /CLKF_P and /CLKF_N respectively generated at /CLK_PE generation circuit 512 and /CLK_NE generation circuit 514.
CQP generation circuit 518 includes a three-input NAND gate 5181, two-input NAND gates 5182 and 5183 and an inverter 5184.
CQP generation circuit 518 generates control clock CQP based on signals /CLK_NE and /CLK_PE when internal signal DOE is at H level. Control clock CQP goes to H level in response to the rise of signal /CLK_PE when signal /CLK_NE is at H level, and thereafter goes to L level in response to the fall of signal /CLK_NE.
In the following, the operation of CQP generation circuit 518 will be described.
In the following description, assuming that internal signal DOE is always at H level, first, signals /CLK_NE and /CLK_PE are respectively at H and L levels. At this point, the output node of NAND gate 5182 is at H level, the output node of NAND gate 5181 is at L level, and the output node of NAND gate 5183 is at H level. Therefore control clock CQP is at L level. In this state, when signal /CLK_PE goes to H level, the output node of NAND gate 5183 goes to L level and control clock CQP goes to H level. Here, the state of the output nodes of NAND gates 5181 and 5182 remains unchanged with the changed state of control signal /CLK_PE, and control clock CQP is held at H level.
Next, in this state, when signal /CLK_NE goes to L level, the output node of NAND gate 5181 goes to H level and the output node of NAND gate 5182 goes to L level. Then, the output node of NAND gate 5183 is inverted to H level and control clock CQP goes to L level.
Thereafter, even if signal /CLK_NE goes to H level again, the state of the output node of each NAND gate remains unchanged and control clock CQP is held at L level. Thereafter when signal /CLK_PE goes to L level, the output node of NAND gate 5182 is at H level and the output node of NAND gate 5181 is at L level. As signal /CLK_PE is at L level, however, the output node of NAND gate 5183 is at H level and therefore control clock CQP remains at L level.
CQN generation circuit 520 includes a three-input NAND gate 5201, two-input NAND gates 5202 and 5203 and an inverter 5204.
CQN generation circuit 520 generates control clock CQN based on signals /CLK_PE and /CLK_NE when internal signal DOE is at H level. Control clock CQN goes to H level in response to the rise of signal /CLK_NE when signal /CLK_PE is at H level, and thereafter goes to L level in response to the fall of signal /CLK_PE. The configuration of CQN generation circuit 520 is same as that of CQP generation circuit 518 except that control signals /CLK_PE and /CLK_NE change places. Therefore description thereof will not be repeated.
FIG. 20 is a timing chart collectively showing operation timings of control signals /CLK_PE and /CLK_NE, control clocks CQP and CQN and DLL clock CLKO generated in clock generation circuit 510.
Referring to FIG. 20, DLL clocks CLK_P and CLK_N are respectively shifted backward by time Ta from the rising/falling edges of external clock EXTCLK. Clock generation circuit 510 brings signal /CLK_PE to L level in response to the rising edge of DLL clock CLK_P (reference character {circle around (1)}) and at the same time generates DLL clock CLKO that is a pulse signal (reference character {circle around (2)}). Clock generation circuit 510 then generates control clock CQP going to H level in response to the rise of signal /CLK_PE (reference character {circle around (3)}), and brings control clock CQP to L level in response to the fall of signal /CLK_NE (reference character {circle around (4)}).
It should be noted that DLL clock CLKO is a pulse signal included while signal /CLK_PE is at L level and that control clock CQP is a signal generated correspondingly when signal /CLK_PE goes to H level. More specifically, clock generation circuit 510 generates each signal such that control clock CQP for shifting internal signal QSOE does not overlap with DLL clock CLKO that determines the output timing of data strobe signal DQS generated based on signals QSOE1 and QSOE2 generated by shifting internal signal QSOE. In this manner, clock generation circuit 510 matches the shift timing of signal in the inside of the device to the output timing of signal to the outside of the device. This is applicable to the relation between control clock CQN and DLL clock CLKO.
Note that time Ta has to satisfy Ta greater than Tb+Tc, where Tb represents the propagation time for the read data to be taken into amplifier circuits 362 and 364 and then to reach output data latch circuit 302 in data output circuit 200, and Tc represents the time for data DQ to be output from output data latch circuit 302 to the outside through output driver circuit 304.
FIGS. 21-23 are circuit diagrams showing the configuration of QSOE shift circuit 502 operating in synchronization with control clock CQP generated in clock generation circuit 510.
Referring to FIGS. 21-23, QSOE shift circuit 502 includes an internal circuit 533 including a CQND generation circuit 530 and a CQPD generation circuit 532, a shift circuit 534, and a signal generation circuit 536.
Referring to FIG. 21, CQND generation circuit 530 includes an NAND gate 5302 and an inverter 5304 and generates signals CQND and /CQND by taking in control clock CQN when internal signal DOE is at H level.
CQND generation circuit 532 includes an NAND gate 5322 and an inverter 5324, and similar to CQND generation circuit 530, generates signals CQPD and /CQPD by taking in control clock CQP when internal signal DOE is at H level.
Referring to FIG. 22, shift circuit 534 includes transfer gates 5341-5344 and an inverter 5345.
Transfer gate 5341 includes inverters 5346 and 5348 and an NAND gate 5347. Transfer gate 5342 includes inverters 5349 and 5351 and an NAND gate 5350. Transfer gate 5343 includes inverters 5352 and 5354 and an NAND gate 5353. Transfer gate 5344 includes inverters 5355 and 5357 and an NAND gate 5356.
In shift circuit 534, alternately arranged are transfer gates 5341 and 5343 outputting the signal at the input node to the output node when control clock CQN is at H level and transfer gates 5342 and 5344 outputting the signal at the input node to the output node when control clock CQP is at H level. Signals QSOED0-QSOED3 are generated by shifting internal signal QSOE sequentially, in response to control clocks CQP and CQN as alternately received.
In the following, the specific operation of shift circuit 534 will be described.
In the following, it is assumed that internal signal DOE is always at H level. After internal signal QSOE is output from READ control circuit 400, CQND circuit 530 receives control clock CQN and signal CQND goes to H level (signal /CQND is at L level). Then, inverter 5346 in transfer gate 5341 on the first stage is activated. Inverter 5345 inverts signal QSOE, and inverter 5346 takes in and inverts the inverted signal to output signal QSOED0. At the output node of NAND gate 5347, the inverted signal of signal QSOED0 is output. Note that while signal CQND is at H level, inverter 5348 is inactivated.
When signal CQND goes to L level (signal /CQND is at H level), inverter 5346 is inactivated, inverter 5348 is activated, and inverter 5348 and NAND gate 5347 form a latch. Therefore, the state of signal QSOED0 and at the output node NAND gate 5347 is held. Thereafter, when signal CQPD goes to H level (signal /CQPD is at L level), inverter 5349 is activated at transfer gate 5342 on the second stage. Inverter 5349 inverts the signal output from transfer gate 5341 to output signal QSOED1. At the output node of NAND gate 5350, the inverted signal of signal QSOED1 is output. Note that while signal CQPD is at H level, inverter 5351 is inactivated.
When signal CQPD goes to L level (signal /CQPD is at H level), inverter 5349 is inactivated, inverter 5351 is activated, and inverter 5351 and NAND gate 5350 form a latch. Therefore, the state of signal QSOED1 and at the output node of NAND gate 5350 is held.
Thereafter, also in transfer gates 5343 and 5344, a signal transition takes place in response to control clocks CQN and CQP, and signals QSOED2 and QSOED3 are sequentially output respectively from transfer gates 5343 and 5344. Note that the circuit configurations and performance of transfer gates 5343 and 5344 are same as those of transfer gates 5341 and 5342, respectively. Therefore, descriptions thereof will not be repeated.
In this manner, shift circuit 534 generates signals QSOED0-QSOED3 by sequentially shifting internal signal QSOE output from READ control circuit 400, in synchronization with control clocks CQN and CQP.
Referring to FIG. 23, signal generation circuit 536 includes NOR gates 5361-5365, NAND gates 5366 and 5367, AND gates 5368-5371 and inverters 5372-5375.
Signal generation circuit 536 uses signals QSOED0-QSOED3 formed by sequentially shifting internal signal QSOE and generates signal QSOE1 for determining the preamble period depending on CAS latency (here either 2.0 or 2.5) and signal QSOE2 for determining the period in which a transition of data strobe signal DQS takes place in synchronization with data DQ.
In the following, the signals in signal generation circuit 536 will be described.
A signal OEA20 is at H level from H level of signal QSOED0 input to NOR gate 5361 to L level of signal QSOED2 input to NOR gate 5362.
A signal OEB20 is at H level from H level of signal QSOED1 input to NOR gate 5362 to L level of signal QSOED2 input to NOR gate 5362.
A signal OEA25 is at H level from H level of signal QSOED1 input to NOR gate 5362 to L level of signal QSOED3 input to NOR gate 5363.
A signal OEB25 is at H level from H level of signal QSOED2 input to NOR gate 5363 to L level of signal QSOED3 input to NOR gate 5363.
Here, a signal MCL20 input to AND gates 5368 and 5370 is at H level when CAS latency is 2.0. On the other hand, a signal MCL 25 input to AND gates 5369 and 5371 is at H level when CAS latency is 2.5.
Therefore, when CAS latency is 2.0, signal QSOE1 is formed by signal OEA20 and signal QSOE2 is formed by signal OEB20. On the other hand, when CAS latency is 2.5, signal QSOE1 is formed by signal OEA25 and signal QSOE2 is formed by signal OEB25. The specific signal waveforms of signals QSOE1 and 2 corresponding to internal signal QSOE will be illustrated later with respect to an overall timing chart (when CAS latency CL is 2.5) for each signal in data strobe signal output circuit 500.
FIG. 24 is a circuit diagram showing the configuration of output data generation circuit 504.
Referring to FIG. 24, output data generation circuit 504 includes inverters 5041-5045 and NAND gates 5046-5053.
Output data generation circuit 504 generates signals RDA and /RDA that are original signals for data strobe signal DQS, in synchronization with control clocks CQP and CQN.
Here, since the starting point for data strobe signal DQS is determined depending on CAS latency, it is necessary to select either of control clocks CQP and CQN as a starting point for signals RDA and /RDA depending on CAS latency and to generate signals RDA and /RDA using the selected control clock as a starting point. More specifically, when CAS latency is an integer, control clock CQN should be the starting point, and when CAS latency is a half-integer, control clock CQP should be the starting point. In output data generation circuit 504, the circuit on the stage prior to NAND gate 5050 selects a trigger to generate signals RDA and /RDA either from control clocks CQP or CQN depending on CAS latency.
On the other hand, the circuit on the stage following NAND gate 5051 generates signals RDA and /RDA based on signals QSOE1 and 2 depending on the control clock selected in the circuit on the prior stage.
In the following, the operation of output data generation circuit 504 will be described.
It is assumed that CAS latency is 2.5. When control clock CQP is input, the output node of inverter 5041 goes to L level, whereby the output nodes of NAND gates 5046, 5048 and 5050 go to H level, L level and H level, respectively. Since the output node of NAND gate 5047 is at L level, the state at the output node of NAND gate 5046 is held even if control clock CQP goes to L level after that. Therefore the state at the output node of NAND gates 5048 and 5050 is also held.
Next, when control clock CQN is input, the output node of NAND gate 5047 goes to H level, the output node of NAND gate 5046 goes to L level, and the output node of NAND gate 5048 goes to H level. Here, signal MCL20 input to NAND gate 5049 is always at L level when CAS latency is 2.5, so that the output node of NAND gate 5049 is always at H level. Therefore, the output node of NAND gate 5050 goes from H level to L level.
In this manner, when CAS latency is 2.5, the output node of NAND gate 5050 goes to H level in response to control clock CQP and goes to L level in response to control clock CQN. Similarly, when CAS latency is 2.0, the output node of NAND gate 5050 goes to H level in response to control clock CQN and goes to L level in response to control clock CQP.
In the circuit on the following stages, both NAND gates 5052 and 5053 receive signal QSOE1. When signal QSOE1 is at L level, both signals RDA and /RDA go to L level. When signal QSOE1 is at H level (as shown in a timing chart later, signal QSOE1 goes to H level half cycle before preamble period and is held at H level until the start of postamble period), the signal output from NAND gate 5051 is output as signal RDA through inverter 5043, NAND gate 5052 and inverter 5044 and is also output as signal /RDA through NAND gate 5053 and inverter 5045.
NAND gate 5051 inverts the signal output from NAND gate 5050 when signal QSOE2 is at H level. Therefore, the signal output from NAND gate 5050 is output from output data generation circuit 504 as signal RDA and signal /RDA that is the inverted signal RDA when both signals QSOE1 and 2 are at H level. The waveforms of signals RDA and /RDA will be described later with respect to an overall timing chart (when CAS latency is 2.5) for each signal in data strobe signal output circuit 500.
FIG. 25 is a circuit diagram showing the configuration of output data latch circuit 506.
Referring to FIG. 25, output data latch circuit 506 includes an RES generation circuit 540, a /RDH latch circuit 542 and a /RDL latch circuit 544.
RES generation circuit 540 includes an NOR gate 5402, an inverter 5404 and an NAND gate 5406. /RDH latch circuit 542 includes a clocked inverter 5422 receiving DLL clocks CLKO and /CLKO as clock inputs and signal RDA as an input signal, an NOR gate 5424, and a clocked inverter 5426 operating by receiving a clock input having a phase opposite to clocked inverter 5422. /RDL latch circuit 544 includes a clocked inverter 5442 receiving DLL clocks CLKO and /CLKO as clock inputs and signal /RDA as an input signal, an NOR gate 5444, and a clocked inverter 5446 operating by receiving a clock input having a phase opposite to clocked inverter 5442.
RES generation circuit 540 outputs signal RES at L level when either of signals /RDH and /RDL respectively generated by /RDH latch circuit 542 and /RDL latch circuit 544 goes to H level. More specifically, when either of signals /RDH and /RDL goes to H level, NOR gate 5402 outputs a signal at L level, which is inverted at inverter 5404 and NAND gate 5406, thereby resulting in signal RES at L level. Then, as described later, when signal RES is at L level, signals /RDH and /RDL are latched at /RDH latch circuit 542 and /RDL latch circuit 544, respectively.
/RDH latch circuit 542 inverts signal RDA to be output as signal /RDH to the output node when it receives DLL clock CLKO (DLL clocks CLKO and /CLKO are respectively at H level and L level). Then, when DLL clocks CLKO and /CLKO are inverted, clocked inverter 5442 is inactivated while clocked inverter 5426 is activated. Furthermore, since signals /RDH and /RDL are complementary to each other and signal RES is at L level when signals RDA and /RDA are output from output data generation circuit 504, signal /RDH is latched by NAND gate 5424 and clocked inverter 5426.
Also in /RDL latch circuit 544, signal /RDL is latched in a manner similar to /RDH latch circuit 542. It is noted that the configuration of /RDL latch circuit 544 is same as that of /RDH latch circuit 542 and therefore the description thereof will not be repeated.
In this manner, output data latch circuit 506 latches signals RDA and /RDA output from output data generation circuit 504 by DLL clock CLKO and using DLL clock CLKO as a trigger, also outputs signals /RDH and /RDL to output driver circuit 508.
FIG. 26 is a circuit diagram showing the configuration of output driver circuit 508.
Referring to FIG. 26, output driver circuit 508 includes a P channel MOS transistor 5081, an N channel MOS transistor 5082 and inverters 5083-5085.
When both signals /RDH and /RDL are at H level, the input gates of P channel MOS transistor 5081 and N channel MOS transistor 5082 are respectively at H level and L level, so that the output node has high impedance.
When signals /RDH and /RDL are respectively at H level and L level, the input gates of P channel MOS transistor 5081 and N channel MOS transistor 5082 are respectively at H level and H level, so that the output node is at L level.
When signals /RDH and /RDL are respectively at L level and H level, the input gates of P channel MOS transistor 5081 and N channel MOS transistor 5082 are respectively at L level and L level, so that the output node is at H level.
FIG. 27 is a timing chart illustrating the waveforms of representative signals in data strobe signal output circuit 500 described above.
Referring to FIG. 27, in this timing chart, READ command is read at timing T1 and data DQ starts to be output at timing T6, 2.5 cycles after timing T1. That is, the case where CAS latency is 2.5 is shown.
DLL clock CLK_P is generated shifted backward by time Ta from the rising edge of external clock EXTCLK. DLL clock CLK_N is generated shifted backward by time Ta from the falling edge of external clock EXTCLK.
Signal /CLK_PE falls in response DLL clock CLK_P rising and has a prescribed falling width. Signal /CLK_NE falls in response to DLL clock CLK_N rising and has a prescribed falling width.
Control clock CQP rises in response to signal /CLK_PE rising and falls in response to signal /CLK_NE falling. Control clock CQN rises in response to signal /CLK_NE rising and falls in response to signal /CLK_PE falling.
DLL clock CLKO rises in response to DLL clock CLK_P rising and has half a cycle having a prescribed pulse width. Here, DLL clock CLKO is characterized in that it is generated such that the pulse width is included within the falling range of signals /CLK_PE, /CLK_NE and does not overlap with control clocks CQP, CQN.
Internal signal QSOE received from READ control circuit 400 goes to H level during (burst length BL/2) cycle after receiving READ command at timing T1. Here, burst length BL is set at four and internal signal QSOE goes to L level at timing T5. Signal QSOE1 goes to H level (in the vicinity of timing T3) in response to the next control clock CQP after internal signal QSOE goes to H level, and goes to L level (in the vicinity of timing T9) in response to control clock CQP after (burst length BL/2+1). Signal QSOE2 goes to H level (in the vicinity of timing T4) in response to control clock CQN following control clock CQP that is the starting point of signal QSOE1, and goes to L level (in the vicinity of timing T9) concurrently with signal QSOE1.
Signal RDA may be output when signal QSOE1 is at H level. Signal RDA is at L level when signal QSOE2 is at L level and when signal QSOE2 goes to H level, it repeats rising and falling from the next control clock CQP in synchronization with the rising edges of control clocks CQP and CQN (from the vicinity of timing T5 to the vicinity of timing T9). It is noted that signal RDA is at L level when signal QSOE1 is at L level.
Similar to signal RDA, signal /RDA may be output when signal QSOE1 is at H level and it is complementary to signal RDA while signal QSOE1 is at H level. It is noted that signal /RDA is at L level when signal QSOE1 is at L level.
Signals /RDH and /RDL operate in synchronization with DLL clock CLKO whereas the signals described above operate in synchronization with control clocks CQP and CQN. Signal /RDH is an inverted signal of signal RDA and signal /RDL is an inverted signal of signal /RDA, both of which are synchronized with DLL clock CLKO.
Then, data strobe signal DQS as a final output goes to L level during the preamble period before data DQ starts to be output, as shown, in response to signals /RDH and /RDL, repeats inversion in synchronization with external clock EXTCLK (backward amount Ta of DLL clocks CLK_P, CLK_N is adjusted in such a manner), and goes to L level during the postamble period (timings T4-T10).
As shown in FIG. 13, since DLL clocks CLK_P and CLK_N are supplied at a variety of points, as much as a few mA of current is consumed by charge/discharge of parasitic capacitance on the signal line, the operations of circuits receiving DLL clock and the like. During a data reading operation, the proportion of the current associated with DLL clock to the entire current is low. However, during so-called active-standby in which rows are activated and the column operation is not performed, the entire current is about 20 mA and thus the proportion of the current associated with DLL clock to the entire current is very high.
Here, it is possible to reduce the current associated with DLL clock described above by activating the circuit on the output stage of DLL circuit 100 at the time of receiving READ command and by prohibiting the output of internal clocks CLK_PF and CLK_NF at the time except the data reading operation.
However, since the time from reception of READ command to the actual distribution of DLL clock to each circuit is constant, it is difficult to stably supply DLL clock before data output is started, in case where CAS latency is short or where the operation frequency is high. More particularly, as described above, data strobe signal DQS needs to be provided with a preamble period one cycle before data output, and data strobe signal output circuit 500 needs to be supplied with DLL clock at the earlier stage.
In addition, READ control circuit 400 may sometimes use the internal clock to determine the timing at which the data read from the memory cell array is taken to the data bus pair and may require an internal clock corresponding to the next cycle after receiving READ command. Therefore, READ control circuit 400 also needs to be supplied with an internal clock at the earlier stage.
The present invention is therefore made to solve these problems. An object of the present invention is to provide a semiconductor memory device which allows for lower power consumption during active-standby by appropriately distributing an internal clock for each circuit on the chip.
Another object of the present invention is to provide a semiconductor memory device which allows for lower power consumption during active-standby by appropriately distributing an internal clock for each circuit on the chip and which allows the internal clock to be securely supplied to a prescribed circuit during a data reading operation.
In accordance with the present invention, a semiconductor memory device is provided in which data is input/output in synchronization with a rise and a fall of an external clock. The semiconductor memory device includes: a memory cell array storing data; an internal clock generation circuit generating first and second internal clocks respectively corresponding to the rise and the fall of the external clock in synchronization with the external clock; at least one operation clock output circuit receiving the first and second internal clocks to output the first and second internal clocks respectively as first and second operation clocks in response to an output enabling signal enabling output of the first and second internal clocks; and at least one data output circuit receiving the first and second operation clocks to externally output data read from the memory cell array in synchronization with the first and second operation clocks.
Preferably, the semiconductor memory device further includes at least one signal recovering circuit arranged on a signal path between the internal clock generation circuit and the data output circuit and for recovering a signal level output from the internal clock generation circuit. Each at least one operation clock generation circuit is provided corresponding to each at least one signal recovering circuit and is included in each at least one signal recovering circuit.
Preferably, the semiconductor memory device further includes a data strobe signal output circuit receiving the first and second internal clocks and the first and second operation clocks and generating and externally outputting a data strobe signal indicative of a timing at which the read data is externally output from the data output circuit, based on the first and second internal clocks and the first and second operation clocks. The data strobe signal output circuit includes a signal generation circuit generating the data strobe signal based on the first and second internal clocks and a signal output circuit externally outputting the data strobe signal generated by the signal generation circuit, in synchronization with the first and second operation clocks.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.